1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits and other electronic devices. More particularly, the invention relates to a method for depositing a metal nitride film.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULS) integrated circuits. However, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on processing capabilities. The multilevel interconnect features that lie at the heart of this technology require careful processing of high aspect ratio features, such as vias, lines, contacts, and other interconnects. Reliable formation of these interconnect features is very important to the VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions, i.e., 0.5 .mu.m or less, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, ie., their height divided by width, increases. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, sub-micron features having high aspect ratios.
One such component that faces the difficulties of forming high aspect ratio features are Dynamic random-access memory (DRAM) integrated circuits which are commonly used for storing data in a digital computer. Currently available DRAMs may contain over 16 million cells fabricated on a single crystal silicon chip, where each memory cell generally comprises a single access transistor connected to a trench capacitor. The access transistor is typically disposed above a trench capacitor to minimize the chip space occupied by the DRAM device. The trench capacitor is typically defined by a high aspect ratio trench structure etched in the substrate. The substrate, typically a doped P+ type, serves as the first electrode of the trench capacitor and is typically connected to a ground connection. The interior surfaces of the trench structure are covered by a composite dielectric film, such as a composite film of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2, which serves as the dielectric for the capacitor. The trench structure is typically filled with a doped N+ polysilicon that serves as the second electrode of the capacitor. The access transistor is typically connected to the second electrode of the trench capacitor.
To facilitate construction of increasingly higher density DRAMs with correspondingly smaller-sized memory cells, capacitor structures and materials that can store the charge in smaller chip space are needed. High dielectric constant (HDC) materials (defined herein as having a dielectric constant greater than about 40) have been used successfully in high density trench capacitor structures in DRAMs to store charges. One such HDC material, tantalum oxide, Ta.sub.2 O.sub.5, has become a promising choice for the next generation of high density memory cells. To form Ta.sub.2 O.sub.5 films with high dielectric constants, a Ta.sub.2 O.sub.5 layer is deposited and then annealed to enhance crystallization, thereby increasing the film's dielectric constant. An adhesion/encapsulation layer is deposited between an electrode surface and the Ta.sub.2 O.sub.5 dielectric layer to improve interlayer adhesion of the Ta.sub.2 O.sub.5 dielectric layer to adjacent materials during the anneal process. The adhesion/encapsulation layer also acts as a barrier layer to minimize interlayer diffusion that may cause degradation of the material properties of the device.
Traditional diffusion resistant materials with good adhesion properties, such as titanium nitride (TiN), have been used in integrated circuit manufacturing as liner/barrier layers generally and are currently being used as the adhesion/encapsulation material for the Ta.sub.2 O.sub.5 dielectric layer in DRAMs. However, the use of TiN as the adhesionlencapsulation material for the Ta.sub.2 O.sub.5 dielectric layer has been problematic. One problem with TiN is that TiN has poor diffusion resistance properties at high temperatures, i.e., greater than about 350.degree. C. In particular, it has been observed that TiN fails to prevent diffusion of adjacent materials into the Ta.sub.2 O.sub.5 dielectric layer at temperatures greater than about 600.degree. C. Temperatures greater than about 600.degree. C. are required during the Ta.sub.2 O.sub.5 layer thermal annealing process to generate higher dielectric constants. As such, TiN has not been a completely satisfactory adhesion/encapsulation material for use with Ta.sub.2 O.sub.5. Other traditional materials, such as silicon nitride (SiN) have also been used as adhesion/encapsulation layers in DRAM manufacturing, however, SiN material has had similar material challenges as the TiN material.
Materials such as tantalum nitride (TaN) that have been observed to have greater diffusion resistance and higher thermal stability than TiN have been proposed for use as the adhesion/encapsulation material in DRAM manufacturing. However, TaN is conventionally deposited by reactive physical vapor deposition (PVD) techniques which are not well suited for covering the sides and bottom surfaces of high aspect ratio (&gt;5:1) features, and may require more than one deposition regime to provide adequate coverage. Additionally, gaps may form in the TaN adhesion/encapsulation layer, and the TaN adhesion/encapsulation layer may have uneven thickness, resulting in some regions having insufficient thickness to adequately block diffusion between adjacent layers.
One proposed alternative to the PYD deposition of TaN adhesionlencapsulation layer is to deposit the barrier layer by a chemical vapor deposition (CVD) technique to provide good conformal coverage of substrate features. However, there are few commercially available TaN precursors, and the TaN precursors that are available produce films which have unacceptable levels of contaminants such as carbon and oxygen, and have poor diffusion resistance, low thermal stability, and undesirable film characteristics. Additionally, films deposited from the commercially available TaN precursors may suffer from poor adhesion to adjacent metal and dielectric layers which can cause interlayer defects, such as film delamination.
Therefore, there is a need for an adhesion/encapsulation material with good barrier properties that is useful for forming devices in sub-micron, high aspect ratio features. Particularly, there is a need for a process for depositing an adhesion/encapsulation material conformarly in sub-micron, high aspect ratio features, where the deposited adhesion/encapsulation material has low levels of contamination, and can withstand high temperatures during processing, particularly during annealing treatments of microelectronic devices having high dielectric constant materials.